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1 stack module features ? 64-mbit flash + 16-mbit psram power supply of 2.7v to 3.1v data i/o x16 66-ball cbga package: 8 x 11x 1.0 mm 64-mbit flash features 64-megabit (4m x 16) flash memory 2.7v - 3.1v read/write high performance ? asynchronous access time ? 70, 85 ns sector erase architecture ? eight 4k word sectors with individual write lockout ? 32k word main sectors with individual write lockout typical sector erase time: 32k word sectors ? 500 ms; 4k word sectors ? 100 ms 64m, four plane organization, permitting concurrent read in any of three planes not being programmed/erased ? memory plane a: 16m of memory including eight 4k word sectors ? memory plane b: 16m of memory consisting of 32k word sectors ? memory plane c: 16m of memory consisting of 32k word sectors ? memory plane d: 16m of memory consisting of 32k word sectors suspend/resume feature for erase and program ? supports reading and programming data from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?30 ma active ? 35 a standby 1.8v i/o option reduces overall system power data polling and toggle bit for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization top or bottom boot block configuration available 128-bit protection register common flash interface (cfi) 16-mbit psram features 16-mbit (1m x 16) 2.7v to 3.1v v cc operation 70 ns access time stack module description the at52bc6402a(t) consists of a 64-mbit flash stacked with a 16-mbit psram in a single cbga package. stack module memory contents device memory combination flash/psram read access at52bc6402a(t) 64m flash + 16m psram asynchronous, page mode 64-mbit flash, 16-mbit psram (x16 i/o) at52bc6402a at52bc6402at preliminary rev. 3441b?stkd?11/04
2 at52bc6402a(t) 3441b?stkd?11/04 66c4 ? cbga top view pin configurations a b c d e f g h 1 23456789101112 a20 a16 we psgnd wp lb a18 nc nc nc nc nc a11 a8 reset vpp ub a17 a5 a15 a10 a21 a19 psoe a7 a4 a14 a9 i/o11 a6 a0 a13 i/o15 i/o13 i/o12 i/o9 a3 ce1 gnd i/o14 i/o4 psvcc i/o2 i/o0 a1 oe a12 pswe i/o6 pscs i/o10 i/o8 a2 gnd nc i/o7 i/o5 vcc i/o3 i/o1 psce1 nc nc nc nc nc pin name function a0 - a21 address i/o0 - i/o15 data inputs/outputs ce1 flash chip enable psce1 psram chip enable pscs psram chip select (deep power-down control ? mode pin) oe /p soe flash output enable/psram output enable we /p swe flash write enable/psram write enable lb lower byte control (psram) ub upper byte control (psram) reset flash reset wp flash write protect vpp flash write protection and power supply for accelerated program/erase operation vcc/psvcc flash power supply/psram power supply nc no connect gnd/psgnd device ground/psram ground
3 at52bc6402a(t) 3441b?stkd?11/04 64-mbit flash description the 64-mbit flash memory is divided into multiple sectors and planes for erase opera- tions. the devices can be read or reprogrammed off a single 2.7v power supply, making them ideally suited for in-system programming. the 64-mbit device is divided into four memory planes. a read operation can occur in any of the three planes which is not being programmed or erased. this concurrent oper- ation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. there is no reason to suspend the erase or program operation if the data to be read is in another memory plane. the end of program or erase is detected by data polling or toggle bit. the vpp pin provides data pr otection and faster progra mming and erase times. when the v pp input is below 0.8v, the program and erase functions are inhibited. when v pp is at 1.65v or above, normal program and erase operations can be performed. with v pp at 12.0v, the program and erase operations are accelerated. with v pp at 12v, a six-byte command (enter single pulse program mode) to remove the requirement of entering the three-byte progr am sequence is offered to further improve programming time. after entering the six-byte code, only single pulses on the write con- trol lines are required for writing into the device. this mode (single pulse word program) is exited by powering down the device, by taking the reset pin to gnd or by a high-to-low transition on the v pp input. erase, erase suspend/resume, program sus- pend/resume and read reset commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external pro- gramming code. device operation command sequences: the device powers on in the read mode. command sequences are used to place the device in other operating modes such as program and erase. after the completion of a program or an erase cycle, the device enters the read mode. the command sequences are written by applying a low pulse on the we input with ce low and oe high or by applying a low-going pulse on the ce input with we low and oe high. the address is latched on the falling edge of the we or ce pulse which- ever occurs first. valid data is latched on the rising edge of the we or the ce pulse, whichever occurs first. the addresses used in the command sequences are not affected by entering the command sequences. asynchronous read: the 64-mbit flash is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in pre- venting bus contention. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to read or standby mode, depending upon the state of the control pins.
4 at52bc6402a(t) 3441b?stkd?11/04 erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical ?1?. the entire memory can be erased by using the chip erase command or individual planes or sectors can be erased by using the plane erase or sector erase commands. chip erase: chip erase is a six-bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. after the full chip erase the device will return back to the read mode. the hard- ware reset during chip erase will stop the erase but the data will be of unknown state. any command during chip erase except erase suspend will be ignored. plane erase : as a alternative to a full chip er ase, the device is organized into four planes that can be individually erased. the plane erase command is a six-bus cycle operation. the plane whose address is valid at the sixth falling edge of we will be erased provided none of the sectors within the plane are protected. sector erase: as an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. the sector erase com- mand is a six-bus cycle operation. the sector whose address is valid at the sixth falling edge of we will be erased provided the given sector has not been protected. word programming: the device is programmed on a word-by-word basis. pro- gramming is accomplished via the internal device command register and is a four-bus cycle operation. the programming address and data are latched in the fourth cycle. the device will automatically generate the requ ired internal progr amming pulses. please note that a ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. flexible sector protection: the 64-mbit device offers two sector protection modes, the softlock and the hardlock. the softlock mode is optimized as sector protec- tion for sectors whose content changes fr equently. the hardlock protection mode is recommended for sectors whose content changes infrequently. once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. each sector can be independently programmed for either the softlock or hardlock sector protection mode. at power-up and reset, all sectors have their soft- lock protection mode enabled. softlock and unlock: the softlock protection mode can be disabled by issuing a two-bus cycle unlock command to the selected sector. once a sector is unlocked, its contents can be erased or programmed. to enable the softlock protection mode, a six- bus cycle softlock command must be issued to the selected sector. hardlock and write protect (wp ): the hardlock sector protection mode oper- ates in conjunction with the write protection (wp ) pin. the hardlock sector protection mode can be enabled by issuing a six-bus cycle hardlock software command to the selected sector. the state of the write protect pin affects whether the hardlock protec- tion mode can be overridden. when the wp pin is low and the hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. when the wp pin is high, the hardlock protection mode is overridden and the sector can be unlocked via the unlock command. to disable the hardlock sector protection mode, the chip must be either reset or power cycled.
5 at52bc6402a(t) 3441b?stkd?11/04 figure 1. sector locking state diagram note: 1. the notation [x, y, z] denotes the locking state of a sector. the current locking state of a sector is defined by the state of wp and the two bits of the sector-lock status d[1:0]. table 1. hardlock and softlock protection configurations in conjunction with wp v pp wp hard- lock soft- lock erase/ prog allowed? comments v cc /5v 0 0 0 yes no sector is locked v cc /5v 0 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 0 1 1 no hardlock protection mode is enabled. the sector cannot be unlocked. v cc /5v 1 0 0 yes no sector is locked. v cc /5v 1 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 1 1 0 yes hardlock protection mode is overridden and the sector is not locked. v cc /5v 1 1 1 no hardlock protection mode is overridden and the sector can be unlocked via the unlock command. v il x x x no erase and program operations cannot be performed. [000] [001] [011] [111] [101] [110] [100] unlocked locked wp = v il =0 wp = v ih =1 power-up/reset default power-up/reset default hardlocked is disabled by wp = v ih = unlock command = softlock command = hardlock command hardlocked ab c c ab ab c c a b c
6 at52bc6402a(t) 3441b?stkd?11/04 sector protection detection: a software method is available to determine if the sector protection softlock or hardlock features are enabled. when the device is in the software product identification mode (see software product identification entry and exit sections) a read from the i/o0 and i/o1 at address location 00002h within a sector will show if the sector is unlocked, softlocked, or hardlocked. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6, and i/o7. all other status bits are don?t care. table 3 on page 11 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the 64-mbit device con- tains a programmable configuration register. the configuration register allows the user to specify the status bit operation. the configuration register can be set to one of two dif- ferent values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is important to note that whether the configuration register is set to a ?00? or to a ?01?, any unsuccessful program or erase operati on requires using the product id exit com- mand to return the device to read mode. the default value (after power-up) for the configuration register is ?00?. using the four-bus cycle set configuration register com- mand as shown in the command definiti on table on page 12, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration register. the value of the configuration register will affect the operation of the i/o7 status bit as described below. data polling: the 64-mbit device features data polling to indicate the end of a pro- gram cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the pro- gram cycle. please see table 3 on page 11 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing data. i/o7 will go high when the device has completed a program or erase operation. once i/o7 has gone high, status informa- tion on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 2 and 3. toggle bit: in addition to data polling, the 64-mbit device provides another method for determining the end of a program or erase cycle. during a program or erase opera- tion, successive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling table 2. sector protection status i/o1 i/o0 sector protection status 0 0 sector not locked 0 1 softlock enabled 1 0 hardlock enabled 1 1 both hardlock and softlock enabled
7 at52bc6402a(t) 3441b?stkd?11/04 and valid data will be read. examining the toggle bit may begin at any time during a pro- gram cycle. please see table 3 on page 11 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 4 and 5 on page 10. erase/program status bit: the device offers a status bit on i/o5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a word pro- gram operation has been successfully performed. the device may also output a ?1? on i/o5 if the system tries to program a ?1? to a location that was previously programmed to a ?0?. only an erase operation can change a ?0? back to a ?1?. if a program (sector erase) command is issued to a protected sector, the protected sector will not be pro- grammed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) operation did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see table 3 on page 11 for more details. v pp status bit: the 64-mbit device provides a status bit on i/o3 that provides infor- mation regarding the voltage level of the vpp pin. during a program or erase operation, if the voltage on the vpp pin is not high enough to perform the desired operation suc- cessfully, the i/o3 status bit will be a ?1?. once the v pp status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. on the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the v pp status bit will output a ?0?. please see table 3 on page 11 for more details. erase suspend/erase resume: the erase suspend command allows the sys- tem to interrupt a sector erase operation and then program or read data from a different sector within the same plane. since this device has a multiple plane architecture, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. after the erase suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase sus- pend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command, which does require the plane address. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is protected. the command sequence for a chip erase suspend and a sec- tor erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming oper ation and then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. after the program- ming operation has been suspended, the system can then read from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume com- mand. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.
8 at52bc6402a(t) 3441b?stkd?11/04 128-bit protection register: the 64-mbit device contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the command definition table on page 12. to lock out block b, the four-bus cycle lock pro- tection register command must be used as shown in the command definition table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the status of block b protection command is given. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the protection register address- ing table on page 13 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not or reading the pr otection register, the product id exit com- mand must be given prior to performing any other operation. cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to inter- face to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to address 55h. the cfi query command can be written when the device is ready to read data or can also be written when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table 4 on page 24. to exit the cfi query mode, the product id exit command must be given. if the cfi query command is given while the part is in the product id mode, then the product id exit command must first be given to return the part to the product id mode. once in the product id mode, it will be necessary to give another product id exit command to return the part to the read mode. hardware data protection: hardware features protect against inadvertent pro- grams to the 64-mbit device in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time-out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) v pp is less than v ilpp . input levels: while operating with a 2.7v to 3.1v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can be driven from 0 to v ccq + 0.6v.
9 at52bc6402a(t) 3441b?stkd?11/04 figure 2. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 3. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 addr = va i/o7 = 1? i/o3, i/o5 = 1? program/erase operation not successful, write product id exit command no no yes yes program/erase operation successful, write product id exit command
10 at52bc6402a(t) 3441b?stkd?11/04 figure 4. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes figure 5. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
11 at52bc6402a(t) 3441b?stkd?11/04 table 3. status bit table i/o7 i/o6 i/o2 configuration register: 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 read address in plane a plane b plane c plane d plane a plane b plane c plane d plane a plane b plane c plane d while programming in plane a i/o7 / 0 data data data to g g l e data data data 1 data data data programming in plane b data i/o7 / 0 data data data to g g l e data data data 1 data data programming in plane c data data i/o7 / 0 data data data to g g l e data data data 1 data programming in plane d data data data i/o7 /0 data data data toggle data data data 1 erasing in plane a 0 / 0 data data data to g g l e data data data to g g l e data data data erasing in plane b data 0 / 0 data data data to g g l e data data data to g g l e data data erasing in plane c data data 0 / 0 data data data to g g l e data data data to g g l e data erasing in plane d data data data 0 / 0 data data data to g g l e data data data to g g l e erase suspended & read erasing sector 1111 1 1 1 1toggletoggletoggletoggle erase suspended & read non- erasing sector data data data data data data data data data data data data erase suspended & program non- erasing sector in plane a i/o7 / 0 data data data to g g l e data data data to g g l e data data data erase suspended & program non- erasing sector in plane b data i/o7 / 0 data data data to g g l e data data data to g g l e data data erase suspended & program non- erasing sector in plane c data data i/o7 / 0 data data data to g g l e data data data to g g l e data erase suspended & program non- erasing sector in plane d data data data i/o7 /0 data data data toggle data data data toggle
12 at52bc6402a(t) 3441b?stkd?11/04 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex). the address format in ea ch bus cycle is as follows: a11 - a0 (hex), a11 - a21 (don?t care). 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. either one of the product id exit commands can be used. 4. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 14 - 17 for deta ils). 5. once a sector is in the hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled. 6. pa is the plane address (a21 - a20). 7. during the fourth bus cycle, the manufacturer code is read from address pa+00000h, the device code is read from address pa+00 001h, and the data in the protection register is read from addresse s 000081h - 000088h. pa (a21 - a20) must specify the same plane ad dress as specified in the third bus cycle. 8. the fast programming option enables the user to program two words in parallel only when v pp = 12v. the addresses, addr0 and addr1, of the two words, d in0 and d in1 , must only differ in address a0. this command should be used for manufacturing purpose only. 9. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 10. the default state (after power-up) of the configuration register is ?00?. 11. any address within the user programmable register region. please see ?protection register addressing table? on page 13. 12. for the at49bv6416, xxxx = 0000h. for the at49bv6416t, xxxx = 3f80h. 13. for the at49bv6416, xxxx = 0000h. for the at49bv6416t, xxxx = 0f80h. command definition (hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 plane erase 6 555 aa aaa 55 555 80 555 aa aaa 55 pa (6) 20 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 30 word program 4 555 aa aaa 55 555 a0 addr d in dual-word program (8) 5 555 aa aaa 55 555 a1 addr0 d in0 addr1 d in1 enter single-pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single-pulse word program mode 1 addr d in sector softlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 40 sector unlock 2 555 aa sa (4) 70 sector hardlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4)(5) 60 erase/program suspend 1 xxx b0 erase/program resume 1 pa (6) 30 product id entry (7) 3 555 aa aaa 55 pa+00555 90 product id exit (3) 3 555 aa aaa 55 555 f0 product id exit (3) 1 xxx fx program protection register ? block b 4 555 aa aaa 55 555 c0 xxxx (12) 8x (11) d in lock protection register ? block b 4 555 aa aaa 55 555 c0 xxxx80 (12) x0 status of block b protection 4 555 aa aaa 55 555 90 xxxx80 (13) d out (9) set configuration register 4 555 aa aaa 55 555 e0 xxx 00/01 (10) cfi query 1 x55 98
13 at52bc6402a(t) 3441b?stkd?11/04 absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages except v pp (including nc pins) with respect to ground ...................................-0.6v to +6.25v v pp input voltage with respect to ground ......................................... 0v to 13.0v all output voltages with respect to ground ...........................-0.6v to v ccq + 0.6v protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0factorya10000001 1factorya10000010 2factorya10000011 3factorya10000100 4userb10000101 5userb10000110 6userb10000111 7userb10001000
14 at52bc6402a(t) 3441b?stkd?11/04 memory organization ? 64-mbit bottom boot plane sector size (words) x16 address range (a21 - a0) a sa0 4k 00000 - 00fff a sa1 4k 01000 - 01fff a sa2 4k 02000 - 02fff a sa3 4k 03000 - 03fff a sa4 4k 04000 - 04fff a sa5 4k 05000 - 05fff a sa6 4k 06000 - 06fff a sa7 4k 07000 - 07fff a sa8 32k 08000 - 0ffff a sa9 32k 10000 - 17fff a sa10 32k 18000 - 1ffff a sa11 32k 20000 - 27fff a sa12 32k 28000 - 2ffff a sa13 32k 30000 - 37fff a sa14 32k 38000 - 3ffff a sa15 32k 40000 - 47fff a sa16 32k 48000 - 4ffff a sa17 32k 50000 - 57fff a sa18 32k 58000 - 5ffff a sa19 32k 60000 - 67fff a sa20 32k 68000 - 6ffff a sa21 32k 70000 - 77fff a sa22 32k 78000 - 7ffff a sa23 32k 80000 - 87fff a sa24 32k 88000 - 8ffff a sa25 32k 90000 - 97fff a sa26 32k 98000 - 9ffff a sa27 32k a0000 - a7fff a sa28 32k a8000 - affff a sa29 32k b0000 - b7fff a sa30 32k b8000 - bffff a sa31 32k c0000 - c7fff a sa32 32k c8000 - cffff a sa33 32k d0000 - d7fff a sa34 32k d8000 - dffff a sa35 32k e0000 - e7fff a sa36 32k e8000 - effff a sa37 32k f0000 - f7fff a sa38 32k f8000 - fffff b sa39 32k 100000 - 107fff b sa40 32k 108000 - 10ffff b sa41 32k 110000 - 117fff b sa42 32k 118000 - 11ffff b sa43 32k 120000 - 127fff b sa44 32k 128000 - 12ffff b sa45 32k 130000 - 137fff b sa46 32k 138000 - 13ffff b sa47 32k 140000 - 147fff b sa48 32k 148000 - 14ffff b sa49 32k 150000 - 157fff b sa50 32k 158000 - 15ffff b sa51 32k 160000 - 167fff b sa52 32k 168000 - 16ffff b sa53 32k 170000 - 177fff b sa54 32k 178000 - 17ffff b sa55 32k 180000 - 187fff b sa56 32k 188000 - 18ffff b sa57 32k 190000 - 197fff b sa58 32k 198000 - 19ffff b sa59 32k 1a0000 - 1a7fff b sa60 32k 1a8000 - 1affff b sa61 32k 1b0000 - 1b7fff b sa62 32k 1b8000 - 1bffff b sa63 32k 1c0000 - 1c7fff b sa64 32k 1c8000 - 1cffff b sa65 32k 1d0000 - 1d7fff b sa66 32k 1d8000 - 1dffff b sa67 32k 1e0000 - 1e7fff b sa68 32k 1e8000 - 1effff b sa69 32k 1f0000 - 1f7fff b sa70 32k 1f8000 - 1fffff c sa71 32k 200000 - 207fff c sa72 32k 208000 - 20ffff c sa73 32k 210000 - 217fff c sa74 32k 218000 - 21ffff c sa75 32k 220000 - 227fff c sa76 32k 228000 - 22ffff c sa77 32k 230000 - 237fff c sa78 32k 238000 - 23ffff c sa79 32k 240000 - 247fff c sa80 32k 248000 - 24ffff c sa81 32k 250000 - 257fff c sa82 32k 258000 - 25ffff c sa83 32k 260000 - 267fff c sa84 32k 268000 - 26ffff c sa85 32k 270000 - 277fff c sa86 32k 278000 - 27ffff c sa87 32k 280000 - 287fff c sa88 32k 288000 - 28ffff c sa89 32k 290000 - 297fff memory organization ? 64-mbit bottom boot (continued) plane sector size (words) x16 address range (a21 - a0)
15 at52bc6402a(t) 3441b?stkd?11/04 c sa90 32k 298000 - 29ffff c sa91 32k 2a0000 - 2a7fff c sa92 32k 2a8000 - 2affff c sa93 32k 2b0000 - 2b7fff c sa94 32k 2b8000 - 2bffff c sa95 32k 2c0000 - 2c7fff c sa96 32k 2c8000 - 2cffff c sa97 32k 2d0000 - 2d7fff c sa98 32k 2d8000 - 2dffff c sa99 32k 2e0000 - 2e7fff c sa100 32k 2e8000 - 2effff c sa101 32k 2f0000 - 2f7fff d sa102 32k 2f8000 - 2fffff d sa103 32k 300000 - 307fff d sa104 32k 308000 - 30ffff d sa105 32k 310000 - 317fff d sa106 32k 318000 - 31ffff d sa107 32k 320000 - 327fff d sa108 32k 328000 - 32ffff d sa109 32k 330000 - 337fff d sa110 32k 338000 - 33ffff d sa111 32k 340000 - 347fff d sa112 32k 348000 - 34ffff memory organization ? 64-mbit bottom boot (continued) plane sector size (words) x16 address range (a21 - a0) d sa113 32k 350000 - 357fff d sa114 32k 358000 - 35ffff d sa115 32k 360000 - 367fff d sa116 32k 368000 - 36ffff d sa117 32k 370000 - 377fff d sa118 32k 378000 - 37ffff d sa119 32k 380000 - 387fff d sa120 32k 388000 - 38ffff d sa121 32k 390000 - 397fff d sa122 32k 398000 - 39ffff d sa123 32k 3a0000 - 3a7fff d sa124 32k 3a8000 - 3affff d sa125 32k 3b0000 - 3b7fff d sa126 32k 3b8000 - 3bffff d sa127 32k 3c0000 - 3c7fff d sa128 32k 3c8000 - 3cffff d sa129 32k 3d0000 - 3d7fff d sa130 32k 3d8000 - 3dffff d sa131 32k 3e0000 - 3e7fff d sa132 32k 3e8000 - 3effff d sa133 32k 3f0000 - 3f7fff d sa134 32k 3f8000 - 3fffff memory organization ? 64-mbit bottom boot (continued) plane sector size (words) x16 address range (a21 - a0)
16 at52bc6402a(t) 3441b?stkd?11/04 memory organization ? 64-mbit top boot plane sector size (words) x16 address range (a21 - a0) d sa0 32k 00000 - 07fff d sa1 32k 08000 - 0ffff d sa2 32k 10000 - 17fff d sa3 32k 18000 - 1ffff d sa4 32k 20000 - 27fff d sa5 32k 28000 - 2ffff d sa6 32k 30000 - 37fff d sa7 32k 38000 - 3ffff d sa8 32k 40000 - 47fff d sa9 32k 48000 - 4ffff d sa10 32k 50000 - 57fff d sa11 32k 58000 - 5ffff d sa12 32k 60000 - 67fff d sa13 32k 68000 - 6ffff d sa14 32k 70000 - 77fff d sa15 32k 78000 - 7ffff d sa16 32k 80000 - 87fff d sa17 32k 88000 - 8ffff d sa18 32k 90000 - 97fff d sa19 32k 98000 - 9ffff d sa20 32k a0000 - a7fff d sa21 32k a8000 - affff d sa22 32k b0000 - b7fff d sa23 32k b8000 - bffff d sa24 32k c0000 - c7fff d sa25 32k c8000 - cffff d sa26 32k d0000 - d7fff d sa27 32k d8000 - dffff d sa28 32k e0000 - e7fff d sa29 32k e8000 - effff d sa30 32k f0000 - f7fff d sa31 32k f8000 - fffff c sa32 32k 100000 - 107fff c sa33 32k 108000 - 10ffff c sa34 32k 110000 - 117fff c sa35 32k 118000 - 11ffff c sa36 32k 120000 - 127fff c sa37 32k 128000 - 12ffff c sa38 32k 130000 - 137fff c sa39 32k 138000 - 13ffff c sa40 32k 140000 - 147fff c sa41 32k 148000 - 14ffff c sa42 32k 150000 - 157fff c sa43 32k 158000 - 15ffff c sa44 32k 160000 - 167fff c sa45 32k 168000 - 16ffff c sa46 32k 170000 - 177fff c sa47 32k 178000 - 17ffff c sa48 32k 180000 - 187fff c sa49 32k 188000 - 18ffff c sa50 32k 190000 - 197fff c sa51 32k 198000 - 19ffff c sa52 32k 1a0000 - 1a7fff c sa53 32k 1a8000 - 1affff c sa54 32k 1b0000 - 1b7fff c sa55 32k 1b8000 - 1bffff c sa56 32k 1c0000 - 1c7fff c sa57 32k 1c8000 - 1cffff c sa58 32k 1d0000 - 1d7fff c sa59 32k 1d8000 - 1dffff c sa60 32k 1e0000 - 1e7fff c sa61 32k 1e8000 - 1effff c sa62 32k 1f0000 - 1f7fff c sa63 32k 1f8000 - 1fffff b sa64 32k 200000 - 207fff b sa65 32k 208000 - 20ffff b sa66 32k 210000 - 217fff b sa67 32k 218000 - 21ffff b sa68 32k 220000 - 227fff b sa69 32k 228000 - 22ffff b sa70 32k 230000 - 237fff b sa71 32k 238000 - 23ffff b sa72 32k 240000 - 247fff b sa73 32k 248000 - 24ffff b sa74 32k 250000 - 257fff b sa75 32k 258000 - 25ffff b sa76 32k 260000 - 267fff b sa77 32k 268000 - 26ffff b sa78 32k 270000 - 277fff b sa79 32k 278000 - 27ffff b sa80 32k 280000 - 287fff b sa81 32k 288000 - 28ffff b sa82 32k 290000 - 297fff b sa83 32k 298000 -29ffff b sa84 32k 2a0000 - 2a7fff b sa85 32k 2a8000 - 2affff b sa86 32k 2b0000 - 2b7fff b sa87 32k 2b8000 - 2bffff b sa88 32k 2c0000 - 2c7fff b sa89 32k 2c8000 - 2cffff memory organization ? 64-mbit top boot (continued) plane sector size (words) x16 address range (a21 - a0)
17 at52bc6402a(t) 3441b?stkd?11/04 b sa90 32k 2d0000 - 2d7fff b sa91 32k 2d8000 - 2dffff b sa92 32k 2e0000 - 2e7fff b sa93 32k 2e8000 - 2effff b sa94 32k 2f0000 - 2f7fff b sa95 32k 2f8000 - 2fffff a sa96 32k 300000 - 307fff a sa97 32k 308000 - 30ffff a sa98 32k 310000 - 317fff a sa99 32k 318000 - 31ffff a sa100 32k 320000 - 327fff a sa101 32k 328000 - 32ffff a sa102 32k 330000 - 337fff a sa103 32k 338000 - 33ffff a sa104 32k 340000 - 347fff a sa105 32k 348000 - 34ffff a sa106 32k 350000 - 357fff a sa107 32k 358000 - 35ffff a sa108 32k 360000 - 367fff a sa109 32k 368000 - 36ffff a sa110 32k 370000 - 377fff a sa111 32k 378000 - 37ffff a sa112 32k 380000 - 387fff memory organization ? 64-mbit top boot (continued) plane sector size (words) x16 address range (a21 - a0) a sa113 32k 388000 - 38ffff a sa114 32k 390000 - 397fff a sa115 32k 398000 - 39ffff a sa116 32k 3a0000 - 3a7fff a sa117 32k 3a8000 - 3affff a sa118 32k 3b0000 - 3b7fff a sa119 32k 3b8000 - 3bffff a sa120 32k 3c0000 - 3c7fff a sa121 32k 3c8000 - 3cffff a sa122 32k 3d0000 - 3d7fff a sa123 32k 3d8000 - 3dffff a sa124 32k 3e0000 - 3e7fff a sa125 32k 3e8000 - 3effff a sa126 32k 3f0000 - 3f7fff a sa127 4k 3f8000 - 3f8fff a sa128 4k 3f9000 - 3f9fff a sa129 4k 3fa000 - 3fafff a sa130 4k 3fb000 - 3fbfff a sa131 4k 3fc000 - 3fcfff a sa132 4k 3fd000 - 3fdfff a sa133 4k 3fe000 - 3fefff a sa134 4k 3ff000 - 3fffff memory organization ? 64-mbit top boot (continued) plane sector size (words) x16 address range (a21 - a0)
18 at52bc6402a(t) 3441b?stkd?11/04 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. manufacturer code: 001fh; device code: 00d6h ? bottom boot; 00d2h ? top boot. 4. the vpp pin can be tied to v cc . for faster program/erase operations, v pp can be set to 12.0v 0.5v. 5. v ihpp (min) = 1.65v. 6. v ilpp (max) = 0.8v. dc and ac operating range 64-mbit device ? 70, 85 ns operating temperature (case) industrial -40c - 85c v cc power supply 2.7v - 3.6v operating modes mode ce oe we reset v pp (4) ai i/o read v il v il v ih v ih xai d out burst read v il v il v ih v ih xai d out program/erase (3) v il v ih v il v ih v ihpp (5) ai d in standby/program inhibit v ih x (1) xv ih xx high z program inhibit xxv ih v ih x xv il xv ih x xxx x v ilpp (6) output disable x v ih xv ih xhigh z reset xxx v il xx high z product identification software v ih a0 = v il , a1 - a21 = v il manufacturer code (3) a0 = v ih , a1 - a21 = v il device code (3)
19 at52bc6402a(t) 3441b?stkd?11/04 note: 1. in the erase mode, i cc is 35 ma. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v i/o = 0v to v cc 1a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v cc 35 a i cc (1) v cc active current f = 66 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 66 mhz; i out = 0 ma 50 ma i ccrw v cc read while write current f = 66 mhz; i out = 0 ma 50 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a 2.5 v i oh = -400 a 2.4 ac driving levels 2.0v 0.6v 1.5v ac measurement level v 1.8k output pin 30 pf 1.3k cc pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pf v in = 0v c out 812 pf v out = 0v
20 at52bc6402a(t) 3441b?stkd?11/04 asynchronous read cycle waveform (1)(2)(3) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). ac asynchronous read timing characteristics symbol parameter 64-mbit-70 64-mbit-85 units minmaxminmax t acc access, address to data valid 70 85 ns t ce access, ce to data valid 70 85 ns t oe oe to data valid 20 20 ns t df ce , oe high to data float 25 25 ns t ro reset to output delay 150 150 ns output valid i/o0 - i/o15 high z reset oe toe tce address valid tdf toh tacc tro ce a0 - a21 trc
21 at52bc6402a(t) 3441b?stkd?11/04 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as address setup time to we and ce low 0 ns t ah address hold time 20 ns t ds data setup time 20 ns t dh data hold time 0 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns t ds t ah t dh t wp data valid ce i/o0-i/o15 a0 -a21 we t as t ds t dh t wp data valid ce i/o0-i/o15 a0 -a21 we t as t ah
22 at52bc6402a(t) 3441b?stkd?11/04 program cycle waveforms sector, plane or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for plane or sector erase, the address depends on what plane or sector is to be erased. (see note 4 and 6 under command definitions on page 12.) 3. for chip erase, the data should be xx10h, for plane erase, the data should be xx20h, and for sector erase, the data should be xx30h 4. the waveforms shown above use the we controlled ac word load waveforms. program cycle characteristics symbol parameter min typ max units t bp word programming time (v pp = v cc )22s t bpvpp word programming time (v pp > 11.5v) 10 s t sec1 sector erase cycle time (4k word sectors) 100 ms t sec2 sector erase cycle time (32k word sectors) 500 ms t es erase suspend time 15 s t ps program suspend time 10 s input data xxaa ce we i/o0 -i/o15 xx55 xxa0 a0 -a21 addr 555 aaa 555 oe (1) oe (1) xxaa xxaa ce we i/o0 -i/o15 xx55 xx80 a0 -a21 555 555 aaa 555 xx55 note3 aaa note2
23 at52bc6402a(t) 3441b?stkd?11/04 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 20. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 20. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a21 we ce oe i/o7 toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
24 at52bc6402a(t) 3441b?stkd?11/04 table 4. common flash interface definition for 64-mbit device address 64-mbit device comments 10h 0051h ?q? 11h 0052h ?r? 12h 0059h ?y? 13h 0002h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1ah 0000h 1bh 0027h vcc min write/erase 1ch 0031h vcc max write/erase 1dh 00b5h vpp min voltage 1eh 00c5h vpp max voltage 1fh 0004h typ word write ? 16 s 20h 0000h 21h 0009h typ block erase ? 500 ms 22h 0010h typ chip erase, 64,300 ms 23h 0004h max word write/typ time 24h 0000h n/a 25h 0003h max block erase/typ block erase 26h 0003h max chip erase/ typ chip erase 27h 0017h device size 28h 0001h x16 device 29h 0000h x16 device 2ah 0000h multiple byte write not supported 2bh 0000h multiple byte write not supported 2ch 0002h 2 regions, x = 2 2dh 007eh 64k bytes, y = 126 2eh 0000h 64k bytes, y = 126 2fh 0000h 64k bytes, z = 256 30h 0001h 64k bytes, z = 256 31h 0007h 8k bytes, y = 7 32h 0000h 8k bytes, y = 7 33h 0020h 8k bytes, z = 32 34h 0000h 8k bytes, z = 32
25 at52bc6402a(t) 3441b?stkd?11/04 vendor specific extended query 41h 0050h ?p? 42h 0052h ?r? 43h 0049h ?i? 44h 0031h major version number, ascii 45h 0030h minor version number, ascii 46h 008fh bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 0000h top boot or 0001h bottom boot bit 0 ? top (?0?) or bottom (?1?) boot block device undefined bits are ?0? 48h 0000h bit 0 ? 4 word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8 word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? continuos burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 0000h bit 0 ? 4 word page, 0 ? no, 1 ? yes bit 1 ? 8 word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 0080h location of protection register lock byte, the section's first byte 4bh 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 0003h # of bytes in the user prog section of prot register ? 2*n table 4. common flash interface definition for 64-mbit device (continued) address 64-mbit device comments
26 at52bc6402a(t) 3441b?stkd?11/04 16-mbit psram description the device is a 16-mbit 1t/1c psram featured by high-speed operation and super low power consumption. the 16-mbit device adopts one transistor memory cell and is orga- nized as 1,048,576 words by 16 bits. it operates in the extended range of temperatures and supports a wide operating voltage range. the device also supports the deep power- down mode for a super low standby current. features cmos process technology 1m x 16-bit organization ttl compatible and tri-state outputs deep power-down: memory cell data hold invalid data mask function by lb , ub note: 1. t oe ? ub , lb = high:output disable. block diagram product vo l tag e [v] mode power dissipation (max) speed t rc [ns] temp. [ c] (i sb1 )(i dpd )(i cc2 ) 16-mbit psram 2.7 ~ 3.1 cs1 with ub , lb :t oe (1) 85 a 10 a 25 ma 70 -30 ~ 85 memory array 1,024k x 16 i/o1 lb psoe pswe cs2 cs1 ub data i/o buffer sense amp write driver i/o8 i/o9 i/o16 row decoder block decoder column decoder pre decoder add input buffer a0 a19 control logic
27 at52bc6402a(t) 3441b?stkd?11/04 note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ). 2. ub , lb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o1 - i/o8. when ub is low, data is written or read to the upper byte, i/o9 - i/o116. note: 1. v il = -1.5v for pulse width less than 10 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to v cc +0.3 v v cc power supply -0.5 to 3.6 v t a ambient temperature -30 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature and time 26010 csec truth table cs1 cs2 pswe psoe lb (2) ub mode i/o pin power i/o1 ~ i/o8 i/o9 ~ i/o16 h (1) h x x x x deselected high-z high-z standby x (1) l x x x x deselected high-z high-z deep power-down l (1) h x x h h output disabled high-z high-z active l h h h x x output disabled high-z high-z active l h h l l h lower byte read d out high-z active l h h l h l upper byte read high-z d out active lhhlll word read d out d out active lhlxlhlower byte write d in high-z active l h l x h l upper byte write high-z d in active lhlxll word write d in d in active recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.7 2.9 3.1 v gnd ground 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.3 (1) 0.6 v
28 at52bc6402a(t) 3441b?stkd?11/04 note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics v cc = 2.7v - 3.1v, t a = -30 c to 85 c (i) symbol parameter test condition min max unit i li input leakage current gnd < v in < v cc -1 1 a i lo output leakage current gnd < v out < v cc , cs1 = v ih , cs2 = v ih , psoe = v ih or pswe = v il -1 1 a i cc operating power supply current cs1 = v il , cs2 = v ih , v in = v ih or v il , i i/o = 0 ma 3ma i cc1 average operating current cs1 < 0.2v, cs2 > v cc - 0.2v v in < 0.2v or v in > v cc - 0.2v, cycle time = 1 s 100% duty, i i/o = 0 ma 5ma i cc2 cs1 = v il , cs2 = v ih , v in = v ih or v il , cycle time = min 100% duty, i i/o = 0 ma 25 ma i sb ttl standby current cs1, cs2 = v ih or ub , lb = v ih 0.5 ma i sb1 standby current (cmos input) cs1 , cs2 > v cc - 0.2v or 85 a i dpd deep power-down current cs2 < gnd +0.2v 10 a v ol output low voltage i ol = 0.5 ma 0.3 v v oh output high voltage i oh = -0.5 ma v cc - 0.3 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, cs1 , cs2, pswe , psoe , ub, lb ) v in = 0v 8 pf c out output capacitance (i/o) v i/o = 0v 10 pf
29 at52bc6402a(t) 3441b?stkd?11/04 ac characteristics v cc = 2.7v ~ 3.1v, t a = -30 c to 85 c (i), unless otherwise specified # symbol parameter 70 ns unit min max read cycle 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 20 ns 5t ba lb , ub access time 20 ns 6t clz chip select to output in low z 10 ns 7t olz output enable to output in low z 5 ns 8t blz lb , ub enable to output in low z 10 ns 9t chz chip disable to output in high z 0 10 ns 10 t ohz out disable to output in high z 0 10 ns 11 t bhz lb , ub disable to output in high z 0 10 ns 12 t oh output hold from address change 5 ns write cycle 13 t wc write cycle time 70 ns 14 t cw chip selection to end of write 60 ns 15 t aw address valid to end of write 60 ns 16 t bw lb , ub valid to end of write 60 ns 17 t as address setup time 0 ns 18 t wp write pulse width 50 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 20 ns 21 t dw data to write time overlap 30 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions t a = -30 c to 85 c (m), unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rising and fall time 5 ns input and output timing reference level 0.5 * v cc output load (see ac test loads figure on page 30)
30 at52bc6402a(t) 3441b?stkd?11/04 ac test loads note: including jig and scope capacitance. power-up sequence 1. supply power. 2. maintain stable power for longer than 200 s. deep power-down entry sequence 1. keep cs2 low state. deep power-down mode is maintained while cs2 is low state. deep power-down exit sequence 1. keep cs2 high state. 2. maintain stable power for longer than 200 s. state diagram d out z 0 = 50 ohm c l = 50 pf (1) r l = 50 ohm v l = 0.5*v ccq standby mode characteristics mode memory cell data standby current [a] wait time [s] standby valid 85 0 deep power-down invalid 10 200 deep power-down entry sequence deep power-down exit sequence power-up sequence power on wait 200 s active standby mode deep power- down mode cs2 = v il cs2 = v ih, cs1 = v ih cs1 = v il, cs2 = v ih cs2 = v il cs2 = v ih
31 at52bc6402a(t) 3441b?stkd?11/04 timing diagrams power-up sequence timing note: power-up time is defined when cs2 is kept high before v cc reaches specified minimum level. in case of cs2 is switched from low level to high level, after v cc reached specified level, it is defined as the deep power-down exit. deep power-down entr y/exit sequence timing note: when switching cs2 from high level to low level, the device will be in the deep power-down. in this case, an internal refr esh stops and the data might be lost. standby mode char acteristics timing deep power-down mode characteristics timing v cc cs1 cs2 normal operation wait 200 s suspend 1 s cs1 cs2 wait 200 s normal operation deep power-down mode standby mode t rc cs1 isb1 deep power-down mode suspend 1 s cs2 idpd
32 at52bc6402a(t) 3441b?stkd?11/04 read cycle 1 (1) , (4) read cycle 2, cs2 = v ih (1) , (2) , (4) read cycle 3, cs2 = v ih (1) , (2) , (4) notes: 1. read cycle occurs whenever a high on the pswe and psoe is low, while ub and/or lb and cs1 and cs2 are in active status. 2. psoe = v il . 3. the t chz , t bhz and t ohz are defined as the time at which the outputs achieve the high impedance state and t olz , t blz and t clz are defined as the time at which the outputs achieve the low impedance state. these are not referenced to output voltage levels. 4. cs1 in high for the standby, low for active. address psoe ub, lb cs1 cs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) v ih address data out previous data data valid t aa t rc t oh t oh t acs t clz (3) data valid t chz (3) high-z cs1 data out
33 at52bc6402a(t) 3441b?stkd?11/04 write cycle 1 (pswe controlled) (1) , (4) , (5) , (9) , (10) write cycle 2 (cs1 controlled) (1) , (4) , (5) , (9) , (10) notes: 1. a write occurs during the overlap of a low cs1 , a low pswe , and a low ub or lb . 2. t wr is measured from the earlier of cs1 or pswe going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the cs1 , lb and ub low transition occur simultaneously with the pswe low transition or after the pswe transition, out- puts remain in a high impedance state. 5. psoe is continuously low (psoe = v il ). 6. q (data out) is the invalid data. 7. q (data out) is the read data of the next address. 8. the t whz is defined as the time at which the outputs achieves the high impedance state. it is not referenced to output voltage levels. 9. cs1 in high for the standby, low for active. 10. do not input data to the i/o pins while they are in the output state. address pswe ub,lb data in cs1 cs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow high-z (2) (6) (7) (3)(8) data valid v ih address pswe ub, lb data in cs1 cs2 data out t cw t aw t bw t wp t as t wr t dw t dh high-z high-z (2) data valid v ih t wc
34 at52bc6402a(t) 3441b?stkd?11/04 write cycle 3 (lb , ub controlled) notes: 1. the t bw is specified from the time satisfied both t as and t wr . 2. although ub and lb are high state, it?s illegal function to change address both cs and pswe are in low state. address pswe ub, lb data in cs1 cs2 t cw t aw t ba t wp t as t wr t dw t dh high-z data valid v ih t wc t wr t as t as
35 at52bc6402a(t) 3441b?stkd?11/04 avoid timing the 16-mbit psram has a timing which is not supported at read operation. if your sys- tem has multiple invalid address signal shorter than t rc during over 48 s at read operation which showed in abnormal timing, it needs a normal read timing at least dur- ing 48 s which showed in avoidable timing(1) or toggle the cs1 to high (> t rc ) one time at least which showed in avoidable timing(2) abnormal timing avoidable timing (1) avoidable timing (2) address pswe cs1 < t rc > 48 s address pswe cs1 > t rc > 48 s address pswe cs1 < t rc > 48 s > t rc
36 at52bc6402a(t) 3441b?stkd?11/04 ordering information t acc (ns) ordering code flash boot block psram package operation range 70 at52bc6402a-70ci bottom 1m x 16 66c6 industrial (-40 to 85 c) at52bc6402at-70ci top 1m x 16 66c6 industrial (-40 to 85 c) 85 AT52BC6402A-85CI bottom 1m x 16 66c6 industrial (-40 to 85 c) at52bc6402at-85ci top 1m x 16 66c6 industrial (-40 to 85 c) package type 66c6 66-ball, plastic chip-size ball grid array package (cbga)
37 at52bc6402a(t) 3441b?stkd?11/04 packaging information 66c6 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 66c6 , 66-ball (12 x 8 array), 11 x 8 x 1.0 mm body, 0.8 mm ball pitch chip-scale ball grid array package (cbga) a 66c6 08/27/03 side view top view bottom view a b c d e f g h 1 2 3 4 5 6 7 8 9 1.20 ref 1.10 ref 10 11 12 marked a1 identifier d e d1 e1 e e ?b a a1 0.12 seating plane c c a1 ball corner common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.0 a1 0.17 ? ? d 10.90 11.00 11.10 d1 8.80 typ e 7.90 8.00 8.10 e1 5.60 typ e 0.80 typ ? b 0.40 typ
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